Dielectric isolation is employed to fabricate semiconductor devices wherein metal-oxide-semiconductor (MOS) or other integrated circuit (IC) elements can be combined with a bipolar junction transistor (BJT), double diffused metal-oxide semiconductor (DMOS) or other high voltage semiconductor device. The DMOS transistor is capable of controlling large currents and is widely regarded as a favored way to control large amounts of power.
A useful process of making dielectric isolated devices was published by Yu Ohata et al. in the IEEE 1987 CUSTOM INTEGRATED CIRCUITS CONFERENCE. The paper titled DIELECTRICALLY ISOLATED INTELLIGENT POWER SWITCH appears on pages 443-446 of the conference publication and sets forth a process for making what is called the Toshiba Corporation Intelligent Power Switch. Here a first N-type semiconductor wafer, having a resistivity selected to optimize the device to be fabricated, is provided with a mirror finish. It is then implanted with donor impurities to create an N+ surface layer. The mirror surface is then oxidized. A second wafer of N+ conductivity is also provided with a mirror finish and this surface oxidized. It was discovered that when such oxidized wafers are washed to develop hydrophilic surfaces, a strong bond forms at room temperature when the wafer faces are placed together. A subsequent heat treatment causes the oxides to join together to form a buried oxide which can act to electrically isolate the material in the two wafers. Typically, the first wafer can then be ground and etched to provide the desired thickness of N type material which exists over an N+ layer that faces the dielectric isolation. The resulting composite semiconductor wafer can be trench etched to isolate a plurality of N type tubs and the trench faces oxidized to complete the dielectric isolation. If desired, the oxidized trenches can be back filled with polycrystalline silicon (polysilicon). To create a vertical DMOS transistor a deep trench can be etched through the N type wafer, its N+ region and the dielectric whereby the second, or N+, wafer is exposed. Then an epitaxial deposition is employed to fill the deep trench with semiconductor material having a resistivity suitable for the DMOS transistor drain and the wafer ground and polished to restore the surface. The gate oxide and gate conductor (typically doped polysilicon) are then located over a first region of the epitaxially deposited silicon. A double diffusion produces the source and channel regions in the surface of the exposed semiconductor. A metal electrode, located over the diffusions so as to short them together in a second region, provides the DMOS source electrode. The drain electrode is available at the N+ substrate formed by the second wafer. Electrically it is the backside of the composite wafer structure.
The region of the composite wafer structure, where the epitaxially backfilled trench is located, will contain a power switch while the adjacent region will contain MOS or BJT devices. These latter devices are conventional and they are isolated by means of diffusions or groove etching of the N and N+ layers in the first wafer.
As shown above, the power switch region can contain a DMOS device which has its drain dedicated to the composite wafer backside. In many cases, the resulting breakdown voltage is not as high as might be desired. For example, the Toshiba Corporation Intelligent Power Switches are rated at 60 and 100 volts for two and twenty ampere devices.